The invention relates to a DRAM memory cell for a DRAM memory device and a method for manufacturing it, the DRAM memory cell having a high reading and storage speed.
A DRAM memory is a dynamic semiconductor memory which, as a memory cell in the memory matrix, contains a memory capacitance which can be connected to a bit line via a selection transistor. If a word line WL is placed at a high voltage level, the selection transistor opens and the memory capacitance is connected to the bit line BL. In this state, the memory cell can be written to by virtue of the fact that the capacitance is discharged or charged in accordance with the desired memory contents. FIG. 1 shows the structure of a typical DRAM memory cell according to the prior art.
In order to achieve a higher degree of integration of memory cells on a semiconductor substrate, structures with vertically arranged selection transistors are increasingly being proposed.
U.S. Pat. No. 5,612,559 describes a semiconductor device with a multiplicity of memory cells. Each memory cell has here a column-shaped, vertically arranged selection transistor which contains a drain region and a source region in a semiconductor substrate column, a current channel which also extends in the vertical direction and is controlled by a control gate electrode which completely surrounds the semiconductor column separated by an oxide layer, extending between the drain and source regions. The control gate electrode which is embodied here is formed by etching back a conductive layer which is composed of doped polysilicon, for example. The control gate electrodes of various memory cells are electrically connected to one another and form the word line for actuating the selection transistor.
The memory cell which is described in U.S. Pat. No. 5,612,599 has the disadvantage that the reading and storage speed of a DRAM memory which is made up of such memory cells is very low. The word line formed from the deposited polysilicon in the memory device described in U.S. Pat. No. 5,612,599 has a high electrical resistance owing to the properties of polysilicon as a material. Furthermore, the cross section of the word line formed from polysilicon is very small in the vicinity of the surrounded semiconductor substrate columns. The small cross section of the word line also results in an increase in the electrical resistance of the word line. Because at least 500 memory cells are connected to one another by means of a word line in a typical DRAM memory, the serial connection of the memory cells by means of the high-impedance word line results overall in a very high resistance. The high resistance of the word line results in high RC transit times and thus to low reading and storage speeds in a DRAM memory of such a design.
A further disadvantage of the structure described in U.S. Pat. No. 5,612,599 consists in the fact that the selection transistor is connected to the bit line by means of contact holes. The manufacture of such contact holes is relatively complex in the manufacturing method and, when the structures are of small size, frequently leads to incorrect contacts which may cause memory cells to fail or even the entire DRAM memory to fail.
The object of the present invention is therefore to provide a DRAM memory cell for a DRAM memory device and a method for manufacturing it which provides a high degree of integration with a simultaneously simple manufacturing process and which ensures a high reading and storage speed of the DRAM memory device.
This object is achieved according to the invention by means of a DRAM memory cell having the features specified in patent claim 1.
The invention provides a DRAM memory cell for a DRAM memory having
a MOSFET selection transistor which has a drain region and a source region in a semiconductor substrate column, a current channel which runs in the vertical direction between the drain and source regions and which can be actuated by a control gate electrode being provided,
a capacitor which is stacked under the MOSFET selection transistor and is electrically connected to the source region in the semiconductor substrate column,
a metal bit line BL which is located above the MOSFET selection transistor and is electrically connected to the drain region in the semiconductor substrate column,
a metal word line WL being provided which directly electrically contacts the control gate electrode of the MOSFET selection transistor and extends perpendicularly with respect to the metal bit line which makes electrical contact in a direct and self-aligning fashion with the drain region.
In a preferred embodiment, the metal word line has a cross section which corresponds to the minimum lithographic structure size F.
The control gate electrode is preferably composed of deposited polysilicon.
In a further preferred embodiment, the control gate electrode extends essentially parallel to the current channel located in the semiconductor substrate column.
Between the control gate electrode and the current channel there is preferably a dielectric layer with a thickness of 4 to 7 nm.
The metal bit line is preferably composed of a patterned multilayer arrangement which has a titanium nitride layer, a tungsten layer and a polysilicon layer.
The capacitor is preferably electrically connected to a corresponding electrode.
The metal bit line and the corresponding electrode preferably make contact with the DRAM memory cell here from two opposite sides.
In one preferred embodiment of the DRAM memory cell according to the invention, the capacitor is electrically connected to the source region by means of vertically extending polysilicon columns.
The polysilicon columns are preferably electrically insulated from the metal word line by a vertically extending first insulating layer.
In a further preferred embodiment, the metal word line is electrically insulated from the corresponding electrode by a second insulating layer.
The bit line of the control gate electrode is preferably electrically insulated by means of a third insulating layer.
In a particularly preferred embodiment of the DRAM memory cell according to the invention, the insulating layers are composed of silicon nitride.
In a further, particularly preferred embodiment, the capacitor has a dielectric layer made of tantalum pentoxide.
The invention also provides a method for manufacturing DRAM memory cells for a DRAM memory device having the following steps:
semiconductor substrate columns are formed on a main carrier oxide layer which is located above a main carrier semiconductor substrate layer,
doping ions are implanted in order to generate a drain region and a source region in the semiconductor substrate columns,
thermal oxidation of the semiconductor substrate columns in order to generate a dielectric gate oxide layer,
a polysilicon layer, a metal layer and an insulating layer are deposited on the oxidized semiconductor substrate column,
anisotropic, chemical, selective dry etching of the deposited layers in order to generate control gate electrodes and metal word lines,
polysilicon columns are formed in order to make electrical contact with the source regions in the semiconductor substrate columns,
a dielectric capacitor layer is deposited on the polysilicon columns formed,
a corresponding electrode is applied to the dielectric capacitor layer,
an auxiliary carrier substrate is provided on the corresponding electrode side,
the main carrier substrate layer and the main carrier oxide layer are removed,
a patterned metal bit line is formed in order to make direct electrical contact, in the semiconductor substrate columns, with the drain regions formed.